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News Release from: Vero Electronics | Subject: 16-slot CompactPCI backplane
Edited by the Engineeringtalk Editorial
Team on 18 August 2000
16-slot CompactPCI backplane to CT/H110
APW Electronics has announced its latest 16 slot CompactPCI backplane, intended for where packaging densities have to be maximised or where the 8 slot limit imposed by the driver is unacceptable
APW Electronics has announced its latest CompactPCI backplane development, a 16 slot unit intended for applications where packaging densities have to be maximised or where the 8 slot limit imposed by the driver technology is an unacceptable restriction on system capability The backplane, conforming to the CT/H110 Computer Telephony Specification, consists of two independent 8 slot backplanes sharing common power and ground planes in a 6U monolithic board
This article was originally published on Engineeringtalk on 23 Jul 2002 at 8.00am (UK)
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To use the extended capability, a front pluggable bridge module is used to connect Slot 8 of the first backplane with Slot 1 of the other, giving a backplane of 14 slots controlled from a single system slot.
The bridge module is electrically transparent and supports 64-bit signals.
The common power and ground planes maximise signal integrity by minimising crosstalk and ground bounce.
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Power Bugs are fitted across the complete width of the unit, giving maximum flexibility in putting power onto the unit.
The backplane supports 32 and 64 bit operation, 3.3 and 5V signalling environments and provides the additional frame ground terminals, required to operate with telecom voltages, as well as logic ground.
The nominal 48VDC telephony voltages require up to 3mm clearance between signal/power plane and ground for safety reasons, so non-populated pins and pads are provided in the appropriate connector areas.
The backplane is divided into five areas.
P1 and P2 conform to the CPCI 2.1 Rev 1.0 Hot Swap specification with various additions: B22 is designated as "Healthy #" and a "JTAG Bus", a test bus consisting of three bussed signals and a daisy chain, is defined in P1.
P3 is an undefined, unbussed area for I/O, with rows z and f allocated to ground and P4 is the H110 TDM bus, bussing data and individual clocks.
P5 is the telephony I/O area, a through-backplane connector to the rear panel transition module.
Neither the P4 nor the P5 connectors are bussed to Slot 1, allowing them to be used for external mass storage connections.
Each backplane supports up to 32 telephone lines, providing real estate on IEEE1101.11 rear plug-up modules for the lines entering the rear of the chassis and their associated lightning and surge protection circuitry.
The backplane integrates analogue and digital signalling, distributes telecom power and ringing voltages as well as the standard CPCI +5V, +3V3, +12V and -12V voltages, and supports geographic slot addressing, shelf enumeration and card identification.
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