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News Release from: Vero Electronics | Subject: CompactPCI backplanes
Edited by the Engineeringtalk Editorial
Team on 21 June 2001
DIN M power slot Hot Swap CompactPCI
backplanes
APW Electronic Solutions has extended its CompactPCI backplane offering with new DIN M single power slot models for applications where N+1 redundancy capability is not required
APW Electronic Solutions has extended its CompactPCI backplane offering with new DIN M single power slot models Power-on to the backplane is via an industry-standard DIN M connector on the left hand side of the backplane outside the CompactPCI area
This article was originally published on Engineeringtalk on 23 Jul 2002 at 8.00am (UK)
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CompactPCI backplanes slim for subracks
APW has further extended its range of CompactPCI backplanes with the introduction of 3 and 6U "reduced width" models, available in two-, three-, four-, five- and six-slot variants.
Dual DIN M Power Slot CompactPCI backplanes
APW Electronic Solutions has extended its CompactPCI backplane offering with new dual DIN M Power Slot versions, available in 3U and 6U versions conforming to PICMG Rev 3.0
A 26-way connector, located next to the DIN M slot, enables access to the APW 300W PSU signal connector, providing user access to PSU status and allowing remote control.
The backplane's power and ground planes are designed to distribute more than 125W/slot, giving a generous safety margin over the 100W/slot defined in the PICMG specification.
Available in heights of 3U and 6U conforming to PICMG Rev 3.0, and in 6U CT/H.110 variants, the latest versions are designed for applications where N+1 redundancy capability is not required.
All models have right hand system slots as standard, support Hot Swap at all slots, are fitted with pull-up terminations on all 64 data lines and are available in 4, 6 and 8 slot versions.
All widths support 66MHz operation, even though 66MHz systems are limited by the PICMG Specification to 5 slots.
All models, including the 3U sizes, support 32 and 64-bit operation and are provided with both 3.3 and 5V power planes.
To guarantee backplane clock skew of less than 1.2ns and provide the highest possible clock signal integrity, all clock lines are matched to less than ñ1mm, run on inside layers and are without vias.
All backplanes have provision for Schottky diode terminations on all signal lines to ensure that the 10ns maximum propagation delay is not violated when a lightly loaded backplane is used in conjunction with strong PCI buffers.
As a further benefit, Schottky diodes also prevent damage to logic devices by clamping negative swinging signals.
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