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PCI-PCI bridge fully compliant with specifications

A GD Technik product story
Edited by the Engineeringtalk editorial team Feb 16, 2001

Pericom's new PI7C7100 is the first triple-port PCI-to-PCI bridge device designed to be fully compliant with the 32-bit, 66MHz implementation of the PCI Local Bus Specification Revision 2.1

Now available from design-in specialist GD Technik is Pericom's new PI7C7100, the industry's first triple-port PCI-to-PCI bridge device designed to be fully compliant with the 32-bit, 66MHz implementation of the PCI Local Bus Specification Revision 2.1.

"The PI7C7100 brings new levels of integration to PCI systems," said Keith Jackson, GD Technik's technical director.

"The triple port device increases the number of PCI slots that can be supported in a system and by integrating the two secondary buses into a single device rather than two PCI-to-PCI bridge ICs valuable board space is conserved." Employing a circular-delta bus architecture, the new PCI-to-PCI bridge features a 32-bit primary and two 32-bit secondary ports.

In addition to supporting synchronous bus transactions between devices on the primary (33/66MHz) and the secondary (33MHz) buses, the PI7C7100 also provides concurrent and independent intra-secondary bus communications which significantly improves overall system performance by reducing traffic on the primary bus.

The PI7C7100 provides arbitration for two sets of 8 secondary bus masters.

Each internal arbiter has programmable two-level priority support and each arbiter can be bypassed with an external arbiter for custom applications.

The new device handles PCI transactions for all I/O and memory commands, Type 1 to Type 0 configuration conversion (downstream only), Type 1 to Type 1 configuration forwarding, and Type 1 to special cycle configuration conversion.

The PI7C7100 supports posted memory write buffers in all directions and implements delayed transactions for all PCI configuration, I/O and memory read commands.

Available now from GD Technik, the new PI7C7100 features full scan test and IEEE 1149.1 JTAG interface support.

It is supplied in a 256-pin plastic BGA package.

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